Standard Cell & Foundation IP Library Characterization Engineer
Work mode: On-site · Location: Austin, United States · Schedule: Full Time.
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Job Description
N2P Systems is seeking an experienced Standard Cell & Foundation IP Library Characterization Engineer to join our enterprise technology delivery team in Austin, TX. At N2P Systems, you will put 10-12 years of hands-on experience with Cadence Virtuoso and Python / TCL / Perl Scripting to work on mission-critical enterprise systems. This is an existing contract, hybrid vacancy with N2P Systems.
We are seeking a Senior Library Characterization Engineer with 6+ years of experience to run characterization flows and generate front-end and back-end design kits for high-performance, low-power, and ultra-high-density standard cell libraries and hard IPs.
N2P Systems uses AI to help screen and assess applications for this role. N2P Systems is an enterprise technology consulting and digital solutions firm operating across Canada, the United States and India.
Key Responsibilities:
• Library & IP Characterization: Run characterization flows for high-performance, low-power, and ultra-high-density standard cell libraries and hard IPs.
• Design Kit Releases: Generate front-end and back-end view design kits for release and ensure complete library QA.
• SPICE & Layout: Run transistor-level simulations (SPICE), direct custom physical layouts, and manage automated library characterization flows.
• High Sigma Analysis: Run high-sigma Monte Carlo simulations and analysis using tools like PrimeSim DR/HSMC and HSA.
• Library QA: Perform crosscheck/SolidoChar checks for library quality assurance and work with PD, RTL, and BE CAD teams to resolve quality issues and hit program milestones.
Required Skills & Qualifications:
• Education: Bachelor's degree in Electrical Engineering, Computer Engineering, or a relevant technical field.
• Experience: 6+ years of experience in a foundry team driving PPA analysis and engineering benchmarking.
• Flows & Tools: Proven experience running characterization flows for IPs, Standard Cells, and Memory compilers using tools like Liberate, Totem, PrimeLib, or equivalent.
• EDA Mastery: Expert-level command of design environments including Cadence Virtuoso, HSPICE, Spectre, and scripting (Python, TCL, Perl, or SKILL).
• Test Chip Tapeout: Track record of participating in test chip tapeouts and owning end-to-end design and sign-off of partitions.