Principal Design Verification Engineer (UVM Expert)

N2P Systems is seeking an experienced Principal Design Verification Engineer (UVM Expert) to join our enterprise technology delivery team in Sunnyvale, CA, USA. At N2P Systems, you will put 10+ years of hands-on experience with SystemVerilog, UVM and Functional Coverage to work on mission-critical enterprise systems. This is an existing contract, hybrid vacancy with N2P Systems.

We are seeking an experienced Principal Design Verification Engineer with 10–15 years of hands-on industry experience for a long-term C2C contract engagement in Sunnyvale, CA. In this role, you will lead and execute complex pre-silicon verification for next-generation ASIC/SoC architectures. Mastery of SystemVerilog and UVM methodology is a strict requirement.

N2P Systems uses AI to help screen and assess applications for this role. N2P Systems is an enterprise technology consulting and digital solutions firm operating across Canada, the United States and India.

Key Responsibilities:

• Verification Architecture & Strategy: Architect, develop, and maintain constrained-random verification environments at IP, subsystem, and SoC levels using SystemVerilog and UVM.

• UVM Component Development: Design scalable, reusable UVM components, including drivers, monitors, agents, scoreboards, predictors, and C/C++ reference models.

• Test Plan & Execution: Author comprehensive verification plans from micro-architecture specs; develop directed and random test suites.

• Coverage Driven Closure: Define and implement functional coverage models, SystemVerilog Assertions (SVA), and code coverage metrics to achieve 100% verification closure prior to tape-out.

• Debug & Gate-Level Simulation: Lead complex root-cause debug of simulation failures (RTL & GLS), partnering closely with RTL Design, Systems, and Firmware teams.

• Flow Automation: Enhance DV methodology and regression infrastructure using Python, Perl, and Tcl scripting.

Required Skills & Qualifications:

• 10–15 years of proven ASIC/SoC design verification experience.

• Deep, expert-level fluency in SystemVerilog and UVM.

• Hands-on experience verifying industry-standard protocols (e.g., PCIe, CXL, UCIe, Ethernet, AMBA AXI/AHB, DDR/LPDDR).

• Proficiency with EDA simulation and debug tools (VCS, Xcelium, Verdi).