Physical Design Engineer

N2P Systems is seeking an experienced Physical Design Engineer to support advanced ASIC and SoC development for a leading technology organization in Sunnyvale, California. This on-site contract opportunity requires strong front-end design experience, particularly in RTL synthesis, synthesis optimization, physical design flows, and placement optimization. The engineer will contribute to achieving performance, power, and area (PPA) targets while improving implementation quality and supporting design convergence throughout the chip development lifecycle.

Key Responsibilities:

• Drive RTL synthesis and synthesis optimization to achieve performance, power, and area (PPA) objectives.

• Perform floorplanning for complex ASIC and SoC designs, considering timing, congestion, and power distribution requirements.

• Collaborate with RTL design engineers to improve RTL quality, synthesis results, and implementation efficiency.

• Analyze synthesized netlists to identify optimization opportunities and improve design quality.

• Work with architecture, RTL, verification, and physical design teams to support design convergence.

• Identify implementation bottlenecks and recommend improvements to facilitate timing closure.

• Participate in design reviews and contribute to improvements in design methodologies and implementation processes.

Required Skills & Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

• 10+ years of industry experience in ASIC/SoC physical design.

• Strong hands-on experience with RTL synthesis and timing optimization.

• Solid experience in floorplanning for advanced technology nodes.

• Strong understanding of netlist optimization and physical implementation methodologies.

• Experience collaborating with RTL and design teams to improve design quality and implementation efficiency.

• Ability to work effectively across multidisciplinary silicon engineering teams.

Preferred Qualifications:

• Experience with industry-standard EDA tools for synthesis and physical design.

• Strong understanding of timing, congestion, power, and area optimization techniques.

• Experience with placement optimization and PPA improvement methodologies.

• Background in high-performance CPU, GPU, AI/ML, or networking SoC designs.